The present invention relates generally to computer graphics, and more specifically to improvements in a Video Graphics Array (`VGA`) controller.
A typical prior art VGA controller has an associated display memory, which consists of an array of dynamic RAM (DRAM) chips. In graphics mode, each pixel on the display has a corresponding display memory location which contains a code (typically 4 or 8 bits) representing the color of that pixel. The CPU controls the display by writing data to the graphics controller. The graphics controller responds to such data by updating the relevant data entries in the display memory.
One of the most commonly executed functions in raster graphics applications is to move and/or modify the stored bit map of the raster image. This function is known as Bit Block Transfer, or BitBlt. In Bit Block Transfer operations, the rectangular bit map for the stored raster image is modified by performing logical operations upon it and a second, different, bit map of the raster image. These logical operations are called RasterOps.
A common sequence of steps that known VGA controllers use to accomplish a Bit Block Transfer using RasterOps is:
(a) Reading the data from a destination bit map so that the data is held in CPU latches (FIG. 4, 90a-d), thus forming the first operand to be sent to the VGA Graphics Controller; PA1 (b) Reading data from a source bit map, which can be stored in system memory or VGA memory; PA1 (c) Writing the source bit map data to the VGA Graphics Controller for use as the second operand; PA1 (d) Performing the RasterOp on the first and second operand; and PA1 (e) Writing the result of the RasterOp to the CPU write data address (destination bit map).
Steps (a) through (e) are repeated for all VGA memory addresses that are encompassed by the destination rectangular bit map. All read and write operations are performed in software by the System CPU.
The use of many steps to perform this reading and writing of destination data is very time consuming when a large amount of data must be modified. A known solution to this problem is a read-modify-write cycle, wherein data is read, modified and rewritten, all in one cycle. Although these cycles are known and have been in use even prior to the implementation of read-modify-write cycles in DRAM, no known VGA controller has implemented a read-modify-write cycle for use in raster graphics operations.